1. Field of the Invention
The present invention relates to a switched capacitor circuit with reduced leakage current, and more particularly, to a switched capacitor circuit in which leakage current is prevented by equalizing voltages at nodes where leakage current tends to flow in a sampling mode, and voltage drop caused by leakage current is minimized in an integrating mode, thereby preventing errors in an output signal.
2. Discussion of Related Art
Generally, a switched capacitor circuit is composed of only a capacitor and a switch, without inductance or resistance. It is widely used in various devices such as an integrator, an analog filter, an analog-digital convertor (ADC) and a digital-analog convertor (DAC) because it can be easily integrated into a single chip in a CMOS process and can reduce power consumption.
FIG. 1A illustrates a conventional switched capacitor circuit 100a using switching devices.
Referring to FIG. 1A, the conventional switched capacitor circuit 100a includes an operational amplifier OP, first to fourth switches S1 to S4, a sampling capacitor CS, and a feedback capacitor CF.
Such a switched capacitor circuit 100a is operated as an integrator, which will be simply described below.
If T is a half of a sampling cycle, when t=(k−1)T, the first and third switches S1 and S3 are on, and thus an input voltage Vin is applied across the sampling capacitor CS. Here, a quantity of electrical charge QCS charged in the sampling capacitor CS is given by Formula 1:QCS=Vin[(k−1)T]·CS  [Formula 1]
Then, when t=kT, the second and fourth switches S2 and S4 are on, and thus the electrical charge charged in the sampling capacitor CS is transferred to the feedback capacitor CF. The transferred electrical charge is added to an output voltage at a time (k−1)T, thereby integrating the output voltage.
That is, when t=kT, a final output voltage Vout is given by Formula 2:
                                          V            out                    ⁡                      (                          k              ·              T                        )                          =                                            V              out                        ⁡                          [                                                (                                      k                    -                    1                                    )                                ·                T                            ]                                -                                                    V                in                            ⁡                              [                                                      (                                          k                      -                      1                                        )                                    ·                  T                                ]                                      ·                                          C                S                                            C                F                                                                        [                  Formula          ⁢                                          ⁢          2                ]            
However, the switched capacitor circuit 100a becomes difficult to switch due to high threshold voltages of the first to fourth switches S1 to S4 as a supplied voltage is gradually decreased.
To solve this problem, as illustrated in FIG. 1B, a switched capacitor circuit 100b in which the first to fourth switches S1 to S4 are substituted with MOS transistors M1 to M5 having low threshold voltages is disclosed.
FIG. 1B illustrates a conventional switched capacitor circuit 100b using MOS transistors.
Referring to FIG. 1B, the conventional switched capacitor circuit 100b includes first to fifth MOS transistors M1 to M5, an operational amplifier OP, a sampling capacitor CS and a feedback capacitor CF.
The first to third MOS transistors M1 to M3 apply an input voltage Vin across the sampling capacitor CS in response to a first signal φ1, and the fourth and fifth transistors M4 and M5 transfer electrical charge charged in the sampling capacitor CS to the feedback capacitor CF in response to a second signal φ2.
Here, the first and second MOS transistors M1 and M2 are complementarily connected to constitute a CMOS transistor in order to widen an input voltage range, and the third to fifth MOS transistors M3 to M5 are NMOS or PMOS transistors.
In the switched capacitor circuit 100b, if the first signal φ1 is 1, the first to third MOS transistors M1 to M3 are on, and the fourth and fifth MOS transistors M4 and M5 are off, and thus an input voltage Vin is charged in the sampling capacitor CS.
However, although the fourth MOS transistor M4 is off, some quantity of leakage current Ids—M4 given by Formula 3 flows in the fourth MOS transistor M4:
                              I                      ds_M            ⁢                                                  ⁢            4                          =                              μ            0                    ⁢                      C                          0              ⁢              X                                ⁢                      W            L                    ⁢                      (                          m              -              1                        )                    ⁢                                    (                              v                T                            )                        2                    ×                      ⅇ                                          (                                                                                                                              V                                                      g_M                            ⁢                                                                                                                  ⁢                            4                                                                          -                                                                                                                                                V                                                  TH_M                          ⁢                                                                                                          ⁢                          4                                                                                                                    )                                            mv                T                                              ×                      (                          1              -                              ⅇ                                                      -                                          V                      m                                                        /                                      v                    T                                                                        )                                              [                  Formula          ⁢                                          ⁢          3                ]            
Here, νT is a thermal voltage, m is a body effect coefficient, μ0 is zero bias mobility, and Cox is a gate oxide capacitance.
In Formula 3, provided that a gate voltage of the fourth MOS transistor M4 is fixed to 0, the leakage current Ids—M4 flowing in the fourth MOS transistor M4 is dependant on the input voltage Vin, and thus leakage current also flows in the first and second MOS transistors M1 and M2, which are in on state.
Here, since the first and second MOS transistors M1 and M2 have non-zero resistances because of their own characteristics, errors in an output signal can result from voltage drop caused by leakage current flowing in the first and second MOS transistors M1 and M2.
Further, if the second signal φ2 is 1, the first to third MOS transistors M1 to M3 are off and the fourth and fifth MOS transistors M4 and M5 are on. In this case, errors in an output signal can also result from voltage drop caused by leakage current in the first to third MOS transistors M1 to M3 and an on-resistance of the fourth and fifth transistors M4 and M5.
Errors in the output signal caused by the leakage current greatly affect the performance of ADCs, DACs and filters, which require low voltage and high precision. Thus, there is need of a means for reducing leakage current in a switched capacitor circuit.